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programmable skew clock buffer (pscb) cy7b9911 roboclock+ cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07209 rev. ** revised september 26, 2001 lock+ features ? all output pair skew <100 ps typical (250 max.) 3.75- to 100-mhz output operation user-selectable output functions ? selectable skew to 18 ns ? inverted and non-inverted ? operation at ? and ? input frequency ? operation at 2x and 4x input frequency (input as low as 3.75 mhz) zero input to output delay 50% duty-cycle outputs outputs drive 50 ? terminated lines low operating current 32-pin plcc/lcc package jitter < 200 ps peak-to-peak (< 25 ps rms) compatible with a pentium ? -based processor functional description the cy7b9911 high speed programmable skew clock buffer (pscb) offers user-selectable control over system clock func- tions. this multiple-output clock driver provides the system in- tegrator with functions necessary to optimize the timing of high-performance computer systems. eight individual ttl drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as 50 ? while delivering minimal and specified output skews and full-swing logic levels. each output can be hardwired to one of nine delay or function configurations. delay increments of 0.6 to 1.5 ns are deter- mined by the operating frequency with outputs able to skew up to 6 time units from their nominal ? zero ? skew position. the com- pletely integrated pll allows external load and transmission line delay effects to be canceled. when this ? zero delay ? capability of the pscb is combined with the selectable output skew functions, the user can create output-to-output delays of up to 12 time units. divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. when combined with the internal pll, these divide functions allow distribution of a low-frequency clock that can be multi- plied by two or four at the clock destination. this facility mini- mizes clock distribution difficulty while allowing maximum sys- tem clock speed and flexibility. pentium is a trademark of intel corporation. logic block diagram pin configuration 7b9911 ? 1 7b9911 ? 2 test fb ref vco and time unit generator fs select inputs (three level) skew select matrix 1 2 3 4323130 17 16 15 14 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 3f0 fs v ref gnd test 2f1 fb 2q1 2q0 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 ccq 2f0 gnd 1f1 1f0 v ccn 1q0 1q1 gnd gnd 3q1 3q0 ccn v ccn v 3f1 4f0 4f1 v ccq v ccn 4q1 4q0 gnd gnd plcc/lcc cy7b9911 filter phase freq det
cy7b9911 roboclock+ document #: 38-07209 rev. ** page 2 of 12 block diagram description phase frequency detector and filter these two blocks accept inputs from the reference frequency (ref) input and the feedback (fb) input and generate correc- tion information to control the frequency of the voltage-con- trolled oscillator (vco). these blocks, along with the vco, form a phase-locked loop (pll) that tracks the incoming ref signal. vco and time unit generator the vco accepts analog control inputs from the pll filter block and generates a frequency that is used by the time unit generator to create discrete time units that are selected in the skew select matrix. the operational range of the vco is de- termined by the fs control pin. the time unit (t u ) is determined by the operating frequency of the device and the level of the fs pin as shown in table 1. skew select matrix the skew select matrix is comprised of four independent sec- tions. each section has two low-skew, high-fanout drivers (xq0, xq1), and two corresponding three-level function select (xf0, xf1) inputs. table 2 below shows the nine possible out- put functions for each section as determined by the function select inputs. all times are measured with respect to the ref input assuming that the output connected to the fb input has 0t u selected. pin definitions signal name i/o description ref i reference frequency input. this input supplies the frequency and timing against which all functional variation is measured. fb i pll feedback input (typically connected to one of the eight outputs). fs i three-level frequency range select. see table 1 . 1f0, 1f1 i three-level function select inputs for output pair 1 (1q0, 1q1). see table 2 . 2f0, 2f1 i three-level function select inputs for output pair 2 (2q0, 2q1). see table 2 3f0, 3f1 i three-level function select inputs for output pair 3 (3q0, 3q1). see table 2 4f0, 4f1 i three-level function select inputs for output pair 4 (4q0, 4q1). see table 2 test i three-level select. see test mode section under the block diagram descriptions. 1q0, 1q1 o output pair 1. see table 2 . 2q0, 2q1 o output pair 2. see table 2 . 3q0, 3q1 o output pair 3. see table 2 . 4q0, 4q1 o output pair 4. see table 2 . v ccn pwr power supply for output drivers. v ccq pwr power supply for internal circuitry. gnd pwr ground. table 1. frequency range select and t u calculation [1] fs [2, 3] f nom (mhz) where n = approximate frequency (mhz) at which t u = 1.0 ns min. max. low 15 30 44 22.7 mid 25 50 26 38.5 high 40 100 16 62.5 u 1 f nom n ----------------------- - = table 2. programmable skew configurations [1] function selects output functions 1f1, 2f1, 3f1, 4f1 1f0, 2f0, 3f0, 4f0 1q0, 1q1, 2q0, 2q1 3q0, 3q1 4q0, 4q1 low low ? 4t u divide by 2 divide by 2 low mid ? 3t u ? 6t u ? 6t u low high ? 2t u ? 4t u ? 4t u mid low ? 1t u ? 2t u ? 2t u mid mid 0t u 0t u 0t u mid high +1t u +2t u +2t u high low +2t u +4t u +4t u high mid +3t u +6t u +6t u high high +4t u divide by 4 inverted notes: 1. for all three-state inputs, high indicates a connection to v cc , low indicates a connection to gnd, and mid indicates an open connection. internal termination circuitry holds an unconnected input to v cc /2. 2. the level to be set on fs is determined by the ? normal ? operating fre- quency (f nom ) of the v co and time unit generator (see logic block diagram). nominal frequency (f nom ) always appears at 1q0 and the other outputs when they are operated in their undivided modes (see tab le 2 ). the frequency appearing at the ref and fb inputs will be f nom when the output connected to fb is undivided. the frequency of the ref and fb inputs will be f nom /2 or f nom /4 when the part is configured for a frequency multiplication by using a divided output as the fb input. 3. when the fs pin is selected high, the ref input must not transition upon power-up until v cc has reached 4.3v.
cy7b9911 roboclock+ document #: 38-07209 rev. ** page 3 of 12 test mode the test input is a three-level input. in normal system oper- ation, this pin is connected to ground, allowing the cy7b9911 to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied low through a 100 ? resistor. this will allow an external tester to change the state of these pins.) if the test input is forced to its mid or high state, the device will operate with its internal phase locked loop disconnected, and input levels supplied to ref will directly control all outputs. relative output to output functions are the same as in normal mode. in contrast with normal operation (test tied low). all outputs will function based only on the connection of their own function select inputs (xf0 and xf1) and the waveform characteristics of the ref input. maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied ............................................ ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +7.0v dc input voltage ............................................ ? 0.5v to +7.0v output current into outputs (low)............................. 64 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma figure 1. typical outputs with fb connected to a zero-skew output [4] t 0 ? 6t u t 0 ? 5t u t 0 ? 4t u t 0 ? 3t u t 0 ? 2t u t 0 ? 1t u t 0 t 0 +1t u t 0 t 0 t 0 t 0 t 0 +2t u +3t u +4t u +5t u +6t u fb input ref input ? 6t u ? 4t u ? 3t u ? 2t u ? 1t u 0t u +1t u +2t u +3t u +4t u +6t u divided invert lm lh (n/a) ml (n/a) mm (n/a) mh (n/a) hl hm ll/hh hh 3fx 4fx (n/a) ll lm lh ml mm mh hl hm hh (n/a) (n/a) (n/a) 1fx 2fx 7b9911 ? 3 operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% note: 4. fb connected to an output selected for ? zero ? skew (i.e., xf1 = xf0 = mid).
cy7b9911 roboclock+ document #: 38-07209 rev. ** page 4 of 12 electrical characteristics over the operating range cy7b9911 parameter description test conditions min. max. unit v oh output high voltage v cc = min., i oh = ? 16 ma 2.4 v v cc = min., i oh = ? 40 ma v ol output low voltage v cc = min., i ol = 46 ma 0.45 v v cc = min., i ol = 46 ma v ih input high voltage (ref and fb inputs only) 2.0 v cc v v il input low voltage (ref and fb inputs only) ? 0.5 0.8 v v ihh three-level input high voltage (test, fs, xfn) [5] min. v cc max. v cc ? 0.85 v cc v v imm three-level input mid voltage (test, fs, xfn) [5] min. v cc max. v cc /2 ? 500 mv v cc /2 + 500 mv v v ill three-level input low voltage (test, fs, xfn) [5] min. v cc max. 0.0 0.85 v i ih input high leakage current (ref and fb inputs only) v cc = max., v in = max. 10 a i il input low leakage current (ref and fb inputs only) v cc = max., v in = 0.4v ? 500 a i ihh input high current (test, fs, xfn) v in = v cc 200 a i imm input mid current (test, fs, xfn) v in = v cc /2 ? 50 50 a i ill input low current (test, fs, xfn) v in = gnd ? 200 a i os output short circuit current [6] v cc = max., v out = gnd (25 c only) ? 250 ma i ccq operating current used by internal circuitry v ccn = v ccq = max., all input selects open com ? l 85 ma i ccn output buffer current per output pair [7] v ccn = v ccq = max., i out = 0 ma input selects open, f max 14 ma pd power dissipation per output pair [8] v ccn = v ccq = max., i out = 0 ma input selects open, f max 78 mw notes: 5. these inputs are normally wired to v cc , gnd, or left unconnected (actual threshold voltages vary as a percentage of v cc ). internal termination resistors hold unconnected inputs at v cc /2. if these inputs are switched, the function and timing of the outputs may glitch and the pll may require an additional t lock time before all datasheet limits are achieved. 6. cy7b9911 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. room tempe rature only. 7. total output current per output pair can be approximated by the following expression that includes device current plus load c urrent: cy7b9911: i ccn = [(4 + 0.11f) + [((835 ? 3f)/z) + (.0022fc)]n] x 1.1 where f = frequency in mhz c = capacitive load in pf z = line impedance in ohms n = number of loaded outputs; 0, 1, or 2 fc = f ? c 8. total power dissipation per output pair can be approximated by the following expression that includes device power dissipatio n plus power dissipation due to the load circuit: cy7b9911: pd = [(22 + 0.61f) + [((1550 ? 2.7f)/z) + (.0125fc)]n] x 1.1 see note 7 for variable definition.
cy7b9911 roboclock+ document #: 38-07209 rev. ** page 5 of 12 capacitance [9] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf note: 9. applies to ref and fb inputs only. tested initially and after any design or process changes that may affect these parameters. ac test loads and waveforms 7b9911 ? 4 7b9911 ? 5 ttl ac test load (cy7b9911) ttl input test waveform (cy7b9911) 5v r1 r2 c l 3.0v 2.0v v th =1.5v 0.8v 0.0v 1ns 1ns 2.0v 0.8v v th =1.5v r1=130 r2=91 c l =30pf (includes fixture and probe capacitance)
cy7b9911 roboclock+ document #: 38-07209 rev. ** page 6 of 12 notes: 10. test measurement levels for the cy7b9911 are ttl levels (1.5v to 1.5v). test conditions assume signal transition times of 2 ns or less and output loading as shown in the ac test loads and waveforms unless otherwise specified. 11. guaranteed by statistical correlation. tested initially and after any design or process changes that may affect these parameters. 12. skew is defined as the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with 30 pf and terminated with 50 ? to 2.06v. 13. t skewpr is defined as the skew between a pair of outputs (xq0 and xq1) when all eight outputs are selected for 0t u . 14. t skew0 is defined as the skew between outputs when they are selected for 0t u . other outputs are divided or inverted but not shifted. 15. there are three classes of outputs: nominal (multiple of t u delay), inverted (4q0 and 4q1 only with 4f0 = 4f1 = high), and divided (3qx and 4qx only in divide-by-2 or divide-by-4 mode). 16. t dev is the output-to-output skew between any two devices operating under the same conditions (v cc ambient temperature, air flow, etc.) 17. t odcv is the deviation of the output from a 50% duty cycle. output pulse width variations are included in t skew2 and t skew4 specifications. 18. specified with outputs loaded with 30 pf. devices are terminated through 50 ? to 2.06v. 19. t pwh is measured at 2.0v. t pwl is measured at 0.8v. 20. t orise and t ofall measured between 0.8v and 2.0v. 21. t lock is the time that is required before synchronization is achieved. this speci- fication is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits. switching characteristics over the operating range [2, 10, 11] cy7b9911 ? 5 cy7b9911 ? 7 parameter description min. typ. max. min. typ. max. unit f nom operating clock frequency in mhz fs = low [1, 2] 15 30 15 30 mhz fs = mid [1, 2] 25 50 25 50 fs = high [1, 2 , 3] 40 100 40 100 t rpwh ref pulse width high 4.0 4.0 ns t rpwl ref pulse width low 4.0 4.0 ns t u programmable skew unit see table 1 see table 1 t skewpr zero output matched-pair skew (xq0, xq1) [12, 13] 0.1 0.25 0.1 0.25 ns t skew0 zero output skew (all outputs) [12, 14] 0.25 0.5 0.3 0.75 ns t skew1 output skew (rise-rise, fall-fall, same class outputs) [12, 15] 0.6 0.7 0.6 1.0 ns t skew2 output skew (rise-fall, nominal-inverted, divided-divided) [12, 15] 0.5 1.2 1.0 1.7 ns t skew3 output skew (rise-rise, fall-fall, different class outputs) [12, 15] 0.5 0.9 0.7 1.4 ns t skew4 output skew (rise-fall, nominal-divided, divided-inverted) [12, 15] 0.5 1.2 1.2 1.9 ns t dev device-to-device skew [11, 16] 1.25 1.65 ns t pd propagation delay, ref rise to fb rise ? 0.5 0.0 +0.5 ? 0.7 0.0 +0.7 ns t odcv output duty cycle variation [17] ? 1.0 0.0 +1.0 ? 1.2 0.0 +1.2 ns t pwh output high time deviation from 50% [18, 19] 2.0 2.5 ns t pwl output low time deviation from 50% [18, 19] 2.5 3 ns t orise output rise time [18, 20] 0.15 1.0 1.5 0.15 1.5 2.5 ns t ofall output fall time [18, 20] 0.15 1.0 1.5 0.15 1.5 2.5 ns t lock pll lock time [21] 0.5 0.5 ms t jr cycle-to-cycle output jitter rms [11] 25 25 ps peak-to-peak [11] 200 200 ps
cy7b9911 roboclock+ document #: 38-07209 rev. ** page 7 of 12 ac timing diagrams t odcv t odcv t ref ref fb q other q inverted q ref divided by 2 ref divided by 4 7b9911 ? 8 t rpwh t rpwl t pd t skewpr, t skew0, 1 t skewpr, t skew0, 1 t skew2 t skew2 t skew3, 4 t skew3, 4 t skew3, 4 t skew1,3, 4 t skew2, 4 t jr
cy7b9911 roboclock+ document #: 38-07209 rev. ** page 8 of 12 operational mode descriptions figure 2 shows the pscb configured as a zero-skew clock buffer. in this mode the 7b9911 can be used as the basis for a low-skew clock distribution tree. when all of the function select inputs (xf0, xf1) are left open, the outputs are aligned and may each drive a terminated transmission line to an indepen- dent load. the fb input can be tied to any output in this con- figuration and the operating frequency range is selected with the fs pin. the low-skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ohms), allows efficient printed circuit board design. figure 3 shows a configuration to equalize skew between met- al traces of different lengths. in addition to low skew between outputs, the pscb can be programmed to stagger the timing of its outputs. the four groups of output pairs can each be programmed to different output timing. skew timing can be adjusted over a wide range in small increments with the appro- priate strapping of the function select pins. in this configuration the 4q0 output is fed back to fb and configured for zero skew. the other three pairs of outputs are programmed to yield dif- ferent skews relative to the feedback. by advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time. in this illustration the fb input is connected to an output with 0-ns skew (xf1, xf0 = mid) selected. the internal pll syn- chronizes the fb and ref inputs and aligns their rising edges to insure that all outputs have precise phase alignment. clock skews can be advanced by 6 time units (t u ) when using an output selected for zero skew as the feedback. a wider range of delays is possible if the output connected to fb is also skewed. since ? zero skew ? , +t u , and ? t u are defined relative to output groups, and since the pll aligns the rising edges of ref and fb, it is possible to create wider output skews by proper selection of the xfn inputs. for example a +10 t u between ref and 3qx can be achieved by connecting 1q0 to fb and setting 1f0 = 1f1 = gnd, 3f0 = mid, and 3f1 = high. (since fb aligns at ? 4 t u and 3qx figure 2. zero-skew and/or zero-delay clock driver system clock l1 l2 l3 l4 length l1 = l2 = l3 = l4 7b9911 ? 9 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test z 0 load load load load ref z 0 z 0 z 0 figure 3. programmable-skew clock driver length l1 = l2 l3 < l2 by 6 inches l4 > l2 by 6 inches 7b9911 ? 10 sys ? tem clock l1 l2 l3 l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test z 0 load load load load ref z 0 z 0 z 0
cy7b9911 roboclock+ document #: 38-07209 rev. ** page 9 of 12 skews to +6 t u , a total of +10 t u skew is realized.) many other con- figurations can be realized by skewing both the output used as the fb input and skewing the other outputs. figure 4 shows an example of the invert function of the pscb. in this example the 4q0 output used as the fb input is pro- grammed for invert (4f0 = 4f1 = high) while the other three pairs of outputs are programmed for zero skew. when 4f0 and 4f1 are tied high, 4q0 and 4q1 become inverted zero phase outputs. the pll aligns the rising edge of the fb input with the rising edge of the ref. this causes the 1q, 2q, and 3q out- puts to become the ? inverted ? outputs with respect to the ref input. by selecting which output is connect to fb, it is possible to have 2 inverted and 6 non-inverted outputs or 6 inverted and 2 non-inverted outputs. the correct configuration would be de- termined by the need for more (or fewer) inverted outputs. 1q, 2q, and 3q outputs can also be skewed to compensate for varying trace delays independent of inversion on 4q. figure 5 illustrates the pscb configured as a clock multiplier. the 3q0 output is programmed to divide by four and is fed back to fb. this causes the pll to increase its frequency until the 3q0 and 3q1 outputs are locked at 20 mhz while the 1qx and 2qx outputs run at 80 mhz. the 4q0 and 4q1 outputs are programmed to divide by two, which results in a 40-mhz wave- form at these outputs. note that the 20- and 40-mhz clocks fall simultaneously and are out of phase on their rising edge. this will allow the designer to use the rising edges of the 1 ? 2 fre- quency and 1 ? 4 frequency outputs without concern for ris- ing-edge skew. the 2q0, 2q1, 1q0, and 1q1 outputs run at 80 mhz and are skewed by programming their select inputs accordingly. note that the fs pin is wired for 80-mhz operation because that is the frequency of the fastest output. figure 6 demonstrates the pscb in a clock divider application. 2q0 is fed back to the fb input and programmed for zero skew. 3qx is programmed to divide by four. 4qx is programmed to divide by two. note that the falling edges of the 4qx and 3qx outputs are aligned. this allows use of the rising edges of the 1 ? 2 frequency and 1 ? 4 frequency without concern for skew mis- match. the 1qx outputs are programmed to zero skew and are aligned with the 2qx outputs. in this example, the fs input is grounded to configure the device in the 15- to 30-mhz range since the highest frequency output is running at 20 mhz. figure 7 shows some of the functions that are selectable on the 3qx and 4qx outputs. these include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. an invert- ed output allows the system designer to clock different sub- systems on opposite edges, without suffering from the pulse asymmetry typical of non-ideal loading. this function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be aligned within the skew spec. the divided outputs offer a zero-delay divider for portions of the system that need the clock to be divided by either two or four, and still remain within a narrow skew of the ? 1x ? clock. without this feature, an external divider would need to be add- ed, and the propagation delay of the divider would add to the skew between the different clock signals. these divided outputs, coupled with the phase locked loop, allow the pscb to multiply the clock rate at the ref input by either two or four. this mode will enable the designer to dis- tribute a low-frequency clock between various portions of the system, and then locally multiply the clock rate to a more suit- able frequency, while still maintaining the low-skew character- istics of the clock driver. the pscb can perform all of the func- tions described above at the same time. it can multiply by two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. figure 4. inverted output connections figure 5. frequency multiplier with skew connections 7b9911 ? 11 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 7b9911 ? 12 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 20 mhz 20 mhz 40 mhz 80 mhz figure 6. frequency divider connections 7b9911 ? 13 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 20 mhz 5 mhz 10 mhz 20 mhz
cy7b9911 roboclock+ document #: 38-07209 rev. ** page 10 of 12 figure 8 shows the cy7b9911 connected in series to con- struct a zero-skew clock distribution tree between boards. de- lays of the downstream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the mas- ter clock source, approximating a zero-delay clock tree. cas- caded clock buffers will accumulate low-frequency jitter be- cause of the non-ideal filtering characteristics of the pll filter. it is recommended that not more than two clock buffers be connected in series. figure 7. multi-function clock driver figure 8. board-to-board clock distribution 20 ? mhz distribution clock 80 ? mhz inverted z 0 7b9911 ? 14 20 ? mhz 80 ? mhz zeroskew 80 ? mhz skewed4ns fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref load load load load z 0 z 0 z 0 system clock z 0 l1 l2 l3 l4 7b9911 ? 15 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 ref fs fb load load load load load test z 0 z 0 z 0 ordering information accuracy (ps) ordering code package name package type operating range 500 cy7b9911 ? 5jc j65 32-lead plastic leaded chip carrier commercial 750 cy7b9911 ? 7jc j65 32-lead plastic leaded chip carrier commercial
cy7b9911 roboclock+ document #: 38-07209 rev. ** page 11 of 12 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams 32-lead plastic leaded chip carrier j65
cy7b9911 roboclock+ document #: 38-07209 rev. ** page 12 of 12 document title: cy7b9911 roboclock+ programmable skew clock buffer (pscb) document number: 38-07209 rev. ecn no. issue date orig. of change description of change * * 1 1 03 4 2 1 2 /21/01 s zv c ha n ge from sp e c nu m b e r: 3 8 -0 0 623 to 3 8- 0 72 0 9

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